Memory components operating on a first in, first out (FIFO) scheme within computer systems can consume significant amounts of power during system operation. Power is consumed each time a read and/or a write to the FIFO memory is executed. Frequently, the FIFO memory stores the same data in consecutive memory addresses. In such cases, reading and writing to memory addresses that are storing the same data as the previous address may be inefficient in terms of power consumption. Accordingly, there may be a need for improved techniques to solve these and other problems.